Hewlett-Packard, Cupertino, California (4 Mar 97)

     
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Computer Technology Lab - Hewlett-Packard, Cupertino, California, USA
     
Formal Verification job openings.
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The Computer Technology Laboratory of Hewlett-Packard is hiring verification 
engineers with skills and interests in Formal Verification.  Successful 
applicants will join a small-but-growing team whose charter is to apply 
Formal Methods to a variety of computer system design problems.
This is an opportunity to develop formal techniques which will have genuine 
impact on the computer industry.
     
Requirements:
     
o  BS, MS or Ph.D degree in EE, CE, CS, CEE or CSEE.
o  Experience in one of the following areas: VLSI, Firmware, board design
   or system simulation.
o  Solid understanding of computer architecture. 
o  Strong communication and teamwork skills.
o  Must be flexible and willing to work in areas other than Formal Methods.
     
In addition to the above requirements, previous experience in some 
of the following areas is preferred:
     
o  Minimum 3 years experience in formal verification.
o  Integrated circuit design, verification, tools and methodologies. 
o  VLSI testing, characterization, diagnostics.
o  CPU board design.
o  RISC Assembly language programming, C programming. 
o  Behavioural modeling.
o  Industrial use of Formal Methods.
     
Successful candidates for this position will become members of an exciting 
lab team responsible for the definition, design, verification and testing 
of our leading edge Mid-Range Computer Servers and High-End Workstations.
     
In addition to a broad benefits package which includes relocation support, 
you'll enjoy the attractive and varied lifestyle available in the Bay Area. 
Cupertino is in the heart of Silicon Valley, close to both San Francisco and 
San Jose. The area offers many recreational choices including the nearby ocean, 
mountains and woods.
     
Hewlett-Packard is one of the world's leaders in the research, development 
and manufacturing of computing and electronic measuring equipment for people 
in business, industry, science, engineering, health care and education. 
HP recently completed its 1996 fiscal year with over $30 billion in total 
revenue, and is currently rated as the number one world-wide supplier of 
Unix Systems and the number two computer company world-wide. The company
has enjoyed steady growth and no unprofitable quarters throughout its history.
     
For immediate consideration, email your resume to:
     
   gyang@cup.hp.com
     
quoting Job Ad "FV-CUP"
     
Hewlett-Packard is an equal employment opportunity employer dedicated to 
affirmative action and workforce diversity.

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IBM, Haifa, Israel (9 Feb 97)

The Verification Technologies area in the IBM Haifa Research Laboratory
has a few openings in the Formal Verification and Processor Verification
groups.
 
We are involved in the research & development of advanced verification
technologies, methodologies and tools, with a high focus on Formal
Verification, including:
 
  - Symbolic Model Checking
  - Coverage-Driven Test Program Generation
  - Specification and Modeling languages
  - Functional Coverage Analysis
 
Our mission is to develop and apply state-of-art functional formal
verification tools to the advantage of IBM processor, ASIC and system
design communities. A cornerstone of our work in Formal Verification is
the development of an industrial-strength, award-winning Model Checking
tool (RuleBase), which is used for H/W design verification across IBM
worldwide. RuleBase has also earned considerable attention in the
industry and academia.
 
Experts in formal methods (specification languages), formal verification
(Model-checking, Theorem-proving), RTL simulation, automatic test
generation are encouraged to apply. Fresh college graduates will be also
considered.
 
 
The IBM Haifa Research Laboratory is an exciting organization
participating in the development of leading edge products and
technologies for IBM. Our environment offers a wide range of activities
as well as synergy between our design and verification teams, as well as
with worldwide IBM design community. In addition, we encourage staff
participation in academic research by attending conferences, driving and
mentoring academic research though the Semiconductor Research Corporation
(SRC) and other funding channels, and maintaining active working/teaching
links with universities.
 
We offer permanent positions as well as visiting (1-2 years) positions in
a lively R&D working environment with competitive salaries and benefits.
 
To apply, please send your resume to:
 
Dr. Yaron Wolfsthal   (yaron@vnet.ibm.com)
Mgr. Formal Verification & Design Automation
IBM Haifa Research Laboratory
MATAM - Advanced Technology Center
Haifa   31905,   ISRAEL
 
Fax.   +972 4 8296 115

Intel, Haifa, Israel (2 Feb 97)

           !!!!!  JOB OPPORTUNITIES  !!!!!
               Future  CAD Technologies
                  Intel, Haifa, Israel


   Future CAD technologies (FCT) is a new and
   growing research group for Logic CAD technologies.
   Our goal is to enable stat-of-the-art Logic
  (functional) design in Intel's future micro-processors.

   We conduct theoretical research and we build
   prototypes. Our role is to "Pave the way" to
   the CAD development team in Intel. We closely interact with
   world-wide academia by driving academic research though
   SRC and other funding channels, we participate in conferences, we
   teach courses at the Israeli Universities
   and we publish papers.

   We are looking for experts (MSc. and Phd or equivalent)
   in the following areas:

   -Synthesis
   -Modeling and Specification languages
   -Formal Verification (Model-checking, Theorem-proving)
   -RTL simulation and testing
   -Automatic test generation

   We offer permanent positions as well as visiting (1-2 years)
   positions.

   The site of Intel in Haifa has a lot to offer to a
   researcher: a leading design team and Intel's Logic
   CAD development teams to co-operate with. In addition,
   a great working environment with excellent salaries and benefits.

   Please send your resume to:

   Dr. Limor Fix
   IDC-41
   Intel Israel (74)
   M.T.M
   Israel

   or by e-mail to: lfix@iil.intel.com

Intel, Hillsboro, Oregon (18 Nov 96)

            ------------------------------
                   Job Opportunities
               Strategic CAD Technology
                  Intel, Oregon, USA
            ------------------------------

Strategic CAD Technology (SCT) is a technology development team in
Design Technology, Intel's internal CAD organization.  SCT's mission
is to provide Intel with a competitive advantage in strategic areas of
CAD technology.  Our focus is on performing research and building
technology to meet the CAD needs of future Intel microprocessors.

We interact with processor-design teams and academia to create
leading-edge solutions for today's and tomorrow's CAD challenges.  We
predict the future needs of processor-design teams and the co-develop
products with the CAD productization teams.

SCT has undergone steady growth since its inception in early 1995.  We
are now one of the top CAD research teams in the world.  Almost all of
the permanent lab members have significant experience in industrial
research or microprocessor design.  In addition to day-to-day
research, we publish papers, write books, file patents, and teach in
universities.

Current areas of research include:
  High-performance circuit design
  Physical design
  High-speed synthesis
  Formal hardware verification
  Dynamic validation

We are located in Hillsboro, Oregon, a suburb of Portland in the
scenic Tualatin Valley about sixty miles east of the beautiful Oregon
coast.  Fishing, hiking, mountain biking, wind-surfing, sailing, and
skiing are all in close proximity to Hillsboro.  For the second year
in a row, Oregon Business Magazine has named Intel the best company to
work for in Oregon.

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In formal verification, we are looking for CAD researchers with a
strong background digital hardware and computer architecture with a
focus in one or more of the following areas:
 o model-checking
 o symbolic-simulation
 o hardware description languages
 o theorem-proving
 o algebraic rewriting
 
At the present time we have opportunities in these areas for permanent
positions, student interns and co-ops, and visiting faculty.

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Intel offers excellent salaries and benefits that include employee
profit sharing and stock ownership plans, tuition reimbursement and
periodic paid sabbaticals.

Intel is an equal opportunity employer and fully supports affirmative
action practices. Intel also supports a drug-free workplace and
requires that all offers of employment be contingent on satisfactory
pre-employment drug test results. 


Interested candidates should send their CV, (preferably in both plain
ASCII text and Postscript), to either:

Carl Seger                 or    Mark Aagaard 
cseger@ichips.intel.com          maagaard@ichips.intel.com

by post:
Carl Seger
Intel Corporation
JFT-102
2111 NE 25th Ave
Hillsboro OR 97124-5961

FAX: 503-264-9359

Job opportunities in Formal Verification at Intel
-------------------------------------------------

Intel Corporation is looking for talented individuals to join
its Formal Verification team of the Merced project (formerly 
known as P7), Intel's next-generation microporcessor, in Santa Clara,
California. 

Although formal verification methods have been in widespread use at 
Intel for several years, sequential formal verification (using model 
checking) has seen its first wide deployment on the Merced project.
This activity has been going on for a year now. During this time
we have trained a large number of engineers in the techniques of
formal specification and proof, made great strides in mastering the 
technology, improving the tools and developing methodologies of usage; 
but most importantly, we have found numerous bugs, some of them very
sneaky, and established FV as a valuable contributor to the quality of 
logic design in Merced. In doing so, we have moved FV from what was
considered a year ago an experimental and unproven technology to a
mainstream activity on Merced. Most of the work, however, is still 
ahead. Merced is a huge design, the biggest Intel has attempted so 
far, featuring a new architecture, microarchitecture and logic, and
FV has a long way to go.

We are looking for a small number of exceptional candidates to own
the formal verification of blocks of Merced logic design. The essence of the
job is simple - finding bugs in RTL design using formal verification. 
The work involves defining a comprehensive test plan for FV, writing it in a 
formal language, and proving the properties using our model checker.
The job involves very close interaction with the design team and other
validation teams - they provide the FVer with the knowledge specific to
the design and help in interpreting the results of formal verification;
with Intel's internal R&D groups which improve and develop FV tools;
and last but not least, with the FV experts in the Merced FV team itself.

The ideal candidate would have an advanced degree (Ph.D. preferred) in
formal validation methods; have experience in hardware validation,
preferably using model checking; and have good understanding of 
computer architecture and microarchitecture. Strong background in
logic design is a plus.

If you are interested, please contact me at vkonrad@mipos2.intel.com
or call 408-765-4299.


Victor Konrad

FV Manager, Merced Project

National Semiconductor, Santa Clara, California (3 Mar 97)

----------------------------------------------------
Job Opportunities in Hardware Formal Verification
         Digital Design Technology
National Semiconductor Corp., Santa Clara, CA, USA
----------------------------------------------------

National Semiconductor is looking for engineers with formal
verification experiences to join the formal verification team
in the Digital Design Technology (DDT) group. The DDT's
role is to provide competitive VLSI design technologies to the 
company's advanced product groups. Formal Verification is one of 
areas that we have been focusing on. 

The formal verification team develops and provides new verification 
techniques and methodologies for complex digital designs, based on 
formal methods, to the company's advanced product groups. The ideal 
candidates for this position need to have the following background.

Qualifications:

 o MS or Ph.D. in EE, CE or CS
   Minimum 2 years experience in hardware formal verification using
   Theorem Proving, Model Checking, Boolean Comparison, or Symbolic 
   Simulation technique, etc. 
 o Strong background of VLSI architecture, design validation/simulation 
   and logic verification
 o Good communication skills

Preferred Experiences:

 o Logic Verification and Synthesis
 o HDL design methodology  
 o Behavioral and RTL modeling
 o Strong programming skills in C/C++ or functional language  

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National Semiconductor offers very good salaries and benefits
including stock ownership plans, employee profit sharing,  
job education and retirement plans.

National Semiconductor is an equal employment opportunity employer and
fully supports affirmative action practices.


If you are interested, please send your resume(in plain text or postscript), 
quoting job Formal Verification, to either:

National Semiconductor Corp.  or  National Semiconductor Corp.     
Joseph Lu                         Att: Maria Alonso                  
2900 Semiconductor Dr.            2900 Semiconductor Dr.             
M/S D3-677                        M/S 14-270                         
Santa Clara, CA 95052             Santa Clara, CA 95052              

E-Mail:jlu@berlioz.nsc.com        E-Mail:mariaa@resumix.nsc.com      
                                  Fax: (408)721-8568 

SRI International, Menlo Park, California (current)