Shalini Ghosh

A short introduction:

I am a Computer Scientist in the Computer Science Laboratory at SRI in Menlo Park. My official mentor at SRI is Dr. Patrick D. Lincoln. I completed my PhD in 2005 at the Computer Engineering Research Center in ECE at the University of Texas at Austin. I worked with Prof. Nur Touba in the Computer Aided Testing (CAT) Laboratory. Previously, I did my MS from the Computer Engineering Department of University of California at Santa Cruz (UCSC). At UCSC, I worked with the Semiconductor Test Group. My MS Thesis advisor was Prof. F. Joel Ferguson.

My research interests are :

• Machine Learning Applications in Natural Language Processing and Signal Processing
  
  • Information extraction from semi-structured text.
    
  • Applications of probabilistic relational models to different domains, e.g., Markov logic networks to natural language processing, Hidden semi-Markov models to signal processing.
    
  • Learning and inference in graphical models.
    
  • Combining rule-based and statistical learning.
    
  • Statistical error analysis in machine learning systems.
    
• Fault Tolerant Computing and Probabilistic Analysis of Dependable Systems
  
  • Probabilistic modeling of failure dependencies in complex cyber-physical systems.
    
  • Resilience and adaptive fault tolerance, statistical analysis of large-scale fault-tolerant systems.
    
  • Fault-tolerant nano-computing, processing signals from nano-sensors.
    
  • Robust routing in wireless sensor networks and other fault-prone networks.
    
  • Error detection/correction using ECC for reliability in dependable systems.
    
  • Joint optimization in VLSI testing (e.g., power, area), design optimization for testability.
    

Selected research projects that I have worked on at SRI:

• Machine reading -- Doing probabilistic reasoning/inference using the Probabilistic Consistency Engine (PCE), an inference engine based on Markov Logic networks, to maintain/enforce consistency in the state of relations/entities extracted by different information extraction systems in the DARPA Machine Reading project. Worked actively for the DARPA evaluation of the machine reading system.
  
• Dependability analysis -- Used PCE for probabilistic modeling of failure dependencies in large complex cyber-physical systems.
  
• Information extraction -- Conducting pilot study for extracting information from technical requirement documents using GATE, PCE and other tools, for automatically generating tests to validate the specifications.
  
• Robust routing -- Applied a probabilistic routing algorithm for efficient robust/resilient routing in wireless sensor networks.
  
• Nano-sensing -- Used Hidden semi-Markov Models (HsMM) for detecting viruses using sensor arrays of nano-wires, as part of DARPA MoleSensing project.
  
• Nano-computing -- Designed dynamic Error Correcting Codes (ECC) for building fault-tolerant architectures at the nano-scale level, as part of DARPA MoleComputing and NSF projects.
  
• Medical diagnosis -- Did statistical analysis of patient and control data from a novel Wii-based Parkinson’s disease detection/calibration system.
  
• Bootstrap learning -- Did fault analysis of the learning system in DARPA Bootstrap Learning project.
  
• Universal spellchecker -- Wrote a hybrid (rule-based and statistical) universal spelling checker for multiple languages, as part of the DARPA Transdec project.
  
• Radar mail -- Implemented a module to predict meeting tasks in emails for DARPA Radar project.
  
• Scientific simulation -- Implemented a simulator for time-of-flight mass spectrometers and Fourier transform infrared spectrometers, as part of DARPA Chemist project.
  
• Cyber physical systems -- Worked on developing resilience workbench for critical applications (e.g., medical remote surgery devices), as part of funded NSF project.
  
• Sea basing -- Formalized the naval sea-basing problem as a variant of the facility-location problem.
  
• Fractionated software -- Started looking into the paradigm of fractionated software in the ONR Fractionated Software project, which aims to bridge the gap between physics and computation.
  

Mentoring:
Research intern, 2011: Tivadar Papai, Ph.D. candidate at University of Rochester (PhD Advisor: Prof. Henry Kautz). Worked on a project for using subjective probabilities given by an expert to train Markov Logic Networks. Currently serving on Tivadar's PhD Thesis Committee.

Contact Information:

Address:	Phone:	E-Mail:
Computer Sciene Laboratory, SRI International, Menlo Park, CA - 94025.	650-862-8614 (Cell) 650-859-3904 (Work)	shalini@csl.sri.com

Professional Information:

PhD Thesis: PDF

MS Thesis: PDF

PUBLICATIONS:

• Markov Logic Networks in Health Informatics[PDF]
  Shalini Ghosh, Natarajan Shankar, Sam Owre, Sean David Gary Swan, Patrick Lincoln
  In Proceedings of ICML-MLGC, 2011.
• Machine Reading Using Markov Logic Networks for Collective Probabilistic Inference[PDF]
  Shalini Ghosh, Natarajan Shankar, Sam Owre
  In Proceedings of ECML-CoLISD, 2011.
• Using the Domain Knowledge of an Expert to Train Markov Logic Networks
  Tivadar Papai, Shalini Ghosh
  Manuscript under preparation.
• Dynamic LDPC Codes for Nanoscale Memory with Varying Fault Arrival Rates[PDF]
  Shalini Ghosh and Patrick D. Lincoln
  Proceedings of Design and Technology of Integrated Systems (DTIS), 2011.
• Real-time Virus Detection in Nanowire Arrays
  Shalini Ghosh, Patrick D. Lincoln, Christian Petersen and Alfonso Valdes
  Manuscript under preparation.
• Query Routing in Wireless Sensor Networks: A Novel Application of Social Query Models
  Shalini Ghosh
  Manuscript under preparation.
• Dynamic Low-Density Parity Check Codes for Fault-tolerant Nano-scale Memory[PDF]
  Shalini Ghosh and Patrick D. Lincoln
  Proceedings of Foundations of Nanoscience (FNANO07), Snowbird, Utah, April 2007
• Low-Density Parity Check Codes for Error Correction in Nanoscale Memory[PDF]
  Shalini Ghosh and Patrick D. Lincoln
  SRI Computer Science Laboratory Technical Report, CSL-0703, September 2007
• Virus Detection in Multiplexed Nanowire Arrays[DOC]
  Shalini Ghosh, Patrick D. Lincoln, Christian Petersen and Alfonso Valdes
  SRI Computer Science Laboratory Technical Report, CSL-0705, October 2007
• Synthesis of Low Power CED Circuits Based on Parity Codes [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the VLSI Test Symposium (VTS), Palm Springs, California, May 2005.
• Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Journal of Low Power Testing (JOLPE), 2005
• Detection Probabilities of Interconnect Breaks: An Analysis [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Special Issue of Integration - the Elsevier VLSI Journal, Vol 38/3, pp 451-465, 2004
• Reducing Power Consumption in Memory ECC Checkers [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the IEEE International Test Conference (ITC), pp. 1322-1331, Charlotte, October 2004.
• Estimating Detection Probabilities of Interconnect Opens using Stuck-at Tests [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Proceedings of the Great Lakes Symposium on VLSI (GLS-VLSI), pp. 254-259, Boston, April 2004. (Runner-up for the Best Student Paper Award)
• Low-power Weighted Pseudo-random BIST Using Special Scan Cells [PDF]
  Shalini Ghosh, Eric McDonald, Sugato Basu and Nur A. Touba
  Proceedings of the Great Lakes Symposium on VLSI (GLS-VLSI), pp. 86-91, Boston, April 2004.
• Weighted Pseudo-Random BIST Using Special Scan Cells with Power Reduction and Weight Set Compression
  Shalini Ghosh, Eric McDonald, Sugato Basu and Nur A. Touba
  Manuscript under preparation for journal submission
• Joint Minimization of Power and Area in Scan Testing by Scan Cell Re-ordering [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2003), Tampa, FL, February 2003.
• An Analysis of Detection Probabilities of Interconnect Opens [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Baskin School of Engineering Technical Report UCSC-CRL-03-17, University of California, Santa Cruz, March 2004.
• Joint Minimization of Power and Area in Scan Testing by Scan Cell Re-ordering [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  CERC Technical Report UT-CERC-TR-NAT02-1, University of Texas, Austin, 2002.
  

  

  Personal Information:

  My husband: Sugato Basu