Shalini Ghosh

A short introduction:

I am a Computer Scientist in the Computer Science Lab at SRI in Menlo Park. I completed my PhD in 2005 at the Computer Engineering Research Center in ECE at the University of Texas at Austin. I worked under Prof. Nur Touba in the Computer Aided Testing (CAT) Lab on VLSI Testing. Previously, I did my MS from the Computer Engineering Department of University of California  at Santa Cruz  (UCSC). At UCSC, I worked with  the Semiconductor Test Group on VLSI Testing. My MS Thesis advisor was Prof. F. Joel Ferguson. My research interests are nano-electronics, power optimization in VLSI testing, concurrent error detection for fault-tolerant systems, relialibility in dependable systems, design for testability, fault modeling and architecture validation. Currently I am also interested in statistical modeling of computational and biological systems.

Contact Information:

Address:	Phone:	E-Mail:
3238 Hoover Street, Redwood City, CA - 94063	650-587-3814 (Home) 650-859-3904 (Work)	shalini@csl.sri.com

Professional Information:

1-page CV: MS Word

Short CV: PDF

PhD Thesis: PDF

MS Thesis: PDF

PUBLICATIONS:

• Dynamic Low-Density Parity Check Codes for Fault-tolerant Nano-scale Memory[PDF]
  Shalini Ghosh and Patrick D. Lincoln
  Proceedings of Foundations of Nanoscience (FNANO07), Snowbird, Utah, April 2007
• Low-Density Parity Check Codes for Error Correction in Nanoscale Memory[PDF]
  Shalini Ghosh and Patrick D. Lincoln
  SRI Computer Science Laboratory Technical Report, CSL-0703, September 2007
• Virus Detection in Multiplexed Nanowire Arrays[DOC]
  Shalini Ghosh, Patrick D. Lincoln, Christian Petersen and Alfonso Valdes
  SRI Computer Science Laboratory Technical Report, CSL-0705, October 2007
• Synthesis of Low Power CED Circuits Based on Parity Codes [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the VLSI Test Symposium (VTS), Palm Springs, California, May 2005.
• Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Journal of Low Power Testing (JOLPE), 2005
• Detection Probabilities of Interconnect Breaks: An Analysis [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Special Issue of Integration - the Elsevier VLSI Journal, Vol 38/3, pp 451-465, 2004
• Reducing Power Consumption in Memory ECC Checkers [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the IEEE International Test Conference (ITC), pp. 1322-1331, Charlotte, October 2004.
• Estimating Detection Probabilities of Interconnect Opens using Stuck-at Tests [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Proceedings of the Great Lakes Symposium on VLSI (GLS-VLSI), pp. 254-259, Boston, April 2004. (One of the finalists for the Best Student Paper Award)
• Low-power Weighted Pseudo-random BIST Using Special Scan Cells [PDF]
  Shalini Ghosh, Eric McDonald, Sugato Basu and Nur A. Touba
  Proceedings of the Great Lakes Symposium on VLSI (GLS-VLSI), pp. 86-91, Boston, April 2004.
• Weighted Pseudo-Random BIST Using Special Scan Cells with Power Reduction and Weight Set Compression
  Shalini Ghosh, Eric McDonald, Sugato Basu and Nur A. Touba
  Manuscript under preparation for journal submission
• Joint Minimization of Power and Area in Scan Testing by Scan Cell Re-ordering [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2003), Tampa, FL, February 2003.
• An Analysis of Detection Probabilities of Interconnect Opens [PDF]
  Shalini Ghosh and F. Joel Ferguson
  Baskin School of Engineering Technical Report UCSC-CRL-03-17, University of California, Santa Cruz, March 2004.
• Joint Minimization of Power and Area in Scan Testing by Scan Cell Re-ordering [PDF]
  Shalini Ghosh, Sugato Basu and Nur A. Touba
  CERC Technical Report UT-CERC-TR-NAT02-1, University of Texas, Austin, 2002.
  

  

  Personal Information:

  My husband Sugato