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Clocked FSM Sythesis considering Real Time Constraints
 by Wolf-Dieter Tiedmann.

Abstract
This paper presents a synthesis technique for synchronous controllers that satisfy real time constraints when realized as a clocked finite state machine that is supplied with a prespecified clock rate. The controller needs to be specified as a Timed Automaton, a representation that could for instance be derived from a timing diagram translation. Result is a Mealy machine graph that generally contains purely time-consuming states.
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