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From Formal Verification to Silicon Compilation
 by Dr. John Rushby, Dr. Natarajan Shankar, J. Joyce, E. Liu, R. Suaya & F. von Henke.

From IEEE Compcon.
San Francisco, CA.
February, 1991.
Pages 450–455.


Abstract
Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. Potential benefits include reduction in the time and costs associated with testing and redesign, improved documentation and ease of modification, and greater confidence in the quality of the final product. This paper reports on an experiment whose main purpose was to identify the difficulties of integrating formal verification with conventional VLSI CAD methodology. Our main conclusion is that the most effective use of formal hardware verification will be at the higher levels of VLSI system design, with lower levels best handled by conventional VLSI CAD tools.
BibTEX Entry
@inproceedings{Joyce&all:compcon,
    AUTHOR = {{J.} Joyce and {E.} Liu and {J.} Rushby and {N.} Shankar and {R.} Suaya and {F.} von Henke},
    TITLE = {From Formal Verification to Silicon Compilation},
    BOOKTITLE = {{IEEE} Compcon},
    YEAR = {1991},
    PAGES = {450--455},
    ADDRESS = {San Francisco, {CA}},
    MONTH = {feb},
    URL = {http://www.csl.sri.com/papers/compcon91/}
}
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