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Correctness of Transformations in High Level Synthesis: Formal Verification
 by Sreeranga P. Rajan.

Abstract
This paper presents a formal approach to address the correctness of transformations in high-level synthesis. The novelty of the work is that a small set of properties that capture a general notion of refinement of control/data-flow graphs used in an industrial synthesis framework have been given, and the properties are independent of the underlying behavior model. We have mechanized the specification and verification of several optimization and refinement transformations used in industrial hardware design. This work has enabled to find and rectify errors in the transformations. Further, the work has led to generalization of transformations typically used in high-level synthesis.
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