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Formal Verification for Fault-Tolerant Architectures: Prolegomena to the design of PVS
 by Sam Owre, Dr. John Rushby, Dr. Natarajan Shankar & Friedrich Von Henke.

Abstract
PVS is the most recent in a series of verification systems developed at SRI. Its design was strongly influenced, and later refined, by our experience in developing formal specifications and mechanically checked verifications for the fault-tolerant architecture, algorithms, and implementations of a model "reliable computing platform" (RCP) for life-critical flight control applications, and by a collaborative project to formally verify the design of a commercial avionics processor called AAMP5. Several of the formal specifications and verifications performed in support of RPC and AAMP5 are individually of considerable complexity and difficulty. But in order to contribute to the over-all gaol, it has often been necessary to modify completed verifications to accommodate changed assumptions or requirements, and people other than the original developer have often needed to understand, review, build on, modify, or extract part of an intricate verification. In this paper, we outline the verifications performed, present the lessons learned, and describe some of the design decisions taken in PVS to better support these large, difficult, iterative, and collaborative verifications.
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